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Predictive Failure Analytics with Optimization for Big Data

Applying data mining and advanced statistical methods to analyze, diagnose and improve manufacturing yield

We present a unique case study of applying data mining and advanced statistical methods to analyze, diagnose and improve manufacturing yield, especially for rare failure event prediction. Intra-die process variations in nanometer technology nodes pose significant challenges to robust design practices. Geometric variations along with random dopant fluctuation effects have had significant impact on Memory functionality/yield. Inaccuracies in the models and variabilities in the process are more pronounced and force us to understand the variability effects in a processor chip with higher accuracy and fidelity and considering more physical effects than ever before. In this case study, we use predictive failure analytics to learn and optimize critical components of the processor, and deal with massive amounts of data using server farms for parallel processing. The technique can handle large numbers of process and design variables which cause mismatches in transistors, demonstrating the capability of high dimensionality, accuracy and efficiency. This increases the confidence level in the functionality and operability of system-on-chip as a whole. The underlying algorithms are generic and can be applied to big data analysis, and in particular, the techniques and framework would be very amenable to a cloud computing architectures for both scalability of processing power and data handling, and for enabling such analysis for organizations that would otherwise not have the means.

Introduction
At present, predicting success or failure of rare events before such events actually occurs is a multi-billion dollar proposal. Research, development and productization of rare event prediction technology is ongoing in the areas of finance, health, manufacturing, supply, business, workforce many other related areas which big data analytics are required. This is not just a mathematicians' dream, but a technology that can be applied in real world applications for reducing cost, improving productivity, optimizing product performance, and optimizing financial outcomes. While the analytics and framework which we developed can be generally applied to many diverse fields, we are here disclosing a unique case study of the technology as applied to Integrated Circuit (IC) Manufacturing and design and which has been successfully commercialized. By observing how the generic algorithms are applied in a specific field, it is easier to understand how it can be applied to multi-faceted applications in the predictive analytics domain.

With the rapid scaling of CMOS technology, die-to-die and intra-die process variation effects are increasing dramatically (Figure 1). To meet the demand of high density memory, designers use the smallest devices and most aggressive design topologies & geometries for SRAM cells (Static random access memory is the main type of memory used in microprocessors, networking chips, cell phone chips, etc.). The drive for small dimension transistors leads to unavoidable manufacturing variations between neighboring transistors of the memory cell, due to variations in transistor physical features & dopants on the atomic scale. Namely, threshold voltage mismatch between neighboring devices can lead to large number of fails in memory designs and can degrade SRAM performance and yield. When combined with other effects such as narrow width effects, SER, temperature and process variations and parasitic transistor resistance, the scaling of SRAMs becomes increasingly difficult due to reduced margins [1-4]; end-of-life effects can further aggravate the situation [1]. The same applies for logic design. In fact, designing for the worst-case is simply not feasible any more. Statistical timing techniques have been used to achieve full-chip and full-process coverage based on high-level models, and enable robust design practices [6]. Furthermore, statistical techniques have been shown to improve quality in the context of at-speed test. To enable full-chip analysis, however, these models do sacrifice accuracy, and deal mainly with 3-sigma estimates.

Figure 1: Classification of variation sources. To ensure chip performance & yield, all of these sources of variation must be considered and controlled.

Accurate modeling and efficient statistical methodologies which can handle large number of variables form the crux of predictive analytics. Memories in microprocessors occupy 50-60% of the area and are critical for storage. In the past, the arena of statistical analysis for logic (latches, decoders etc) and SRAM memory has not been addressed adequately in the context of circuit design, especially when rare event failure estimation is involved; this is true not only from the performance perspective but also from the functional behavior perspective. Hence, there is a need to capture not only average logic delay distributions, but also possible design fails. As the number of elements (e.g. latches) increase in the designs, it is possible that a rare functional fail could occur; this is especially true when we want to guarantee the yield for millions of chips. Furthermore, it is necessary to analyze the yield of the memory design in-situ with the peripheral logic. This raises the need for simultaneous statistical analysis of the memory/logic unit.

In this case study, we employ superfast Monte-Carlo compatible techniques intended for memory analysis to such custom logic applications. We first revisit the methodology and its use as an analysis tool for different designs. We then take concrete examples to demonstrate the methodology for custom logic. Namely, we go over case studies of memory interacting with logic in-terms of the local evaluation circuits undergoing Fast-Read-Before-Write. Finally we conclude with the examples of memory decode logic and hit-logic. Figure 2 provides an overview of the applications under study in terms of the components in commonly used chip design. Recently published work [6] on an IBM POWER8 microprocessor shows close to 4.2B transistors with 12 cores with L2 and shared L3 SRAM Cache memories.

As is the case with state-of-the-art microprocessors, memory units occupy 50-60% of the chip while the logic occupies the rest. Hence, prediction of yields through variability analysis is of prime importance targeting first memory elements and then logic.

Figure 2: Partitioning of logic and memory in state-of-the-art chip design ([7]).

Predictive Analytics for Memory Yield Design And Beyond
Traditionally, the Monte Carlo method has been adopted to estimate yield and fail probabilities of a given design. (F However, with the increasing demand of density and chip-yield requirements, stringent requirements on the fail probability are necessary, which are in the range of 1-per-million or lower making it impossible to rely on traditional statistical methods as illustrated in Figure 3. Also as the number of input variables increases Monte Carlo suffers from extraordinary speed reduction and becomes impractical to be used in rare failure events.

Figure 3: Prior Art: Monte Carlo method and its alternatives can lead to inaccuracies in the yield estimate given the limited number of sample points.

In [4], we proposed mixture importance sampling as a comprehensive and computationally efficient method for purposes of estimating low fail probabilities of SRAM designs. The method relies on adjusting the (natural) Monte Carlo sampling function, to produce more samples in the important region(s) (see Figure 4). It is based on the following fact.

where Ep[Q] is the expected value of Q with respect to the sampling function p(x), g(x) is the distorted sampling function, and p(x) is the natural distribution. The method is theoretically sound, and with the proper choice of g(x), we are able to obtain accurate results with a relatively small number of simulations. We refer the reader to [4] for more details.

Figure 4: Importance sampling helps improve the rate of sampling in the important regions as opposed to traditional Monte Carlo.

For SRAM cells, important metrics such as read/write margins, stability and performance are subjected to process variation and this can degrade the yield. Figure 5 illustrates a schematic sketch of a 6-transistor SRAM cell; often, to enable improved yield, the cell and logic supplies are separated. Here, we allocate Vcs to cell supply and Vdd to the bitline logic. We also enlist two different cases: (1) wordline connected to Vdd, and (2) wordline connected to Vcs. We then rely on our methodology to study the yield under different dual supply topologies and conditions [8]. Figure 6 illustrates an example of model-to-hardware corroboration for the case 1 for combined stability results. Similarly case 2 can be handled. The same technique can be applied to logic.

Figure 5: Schematic of an SRAM cell, and possible dual supply scenarios.

Figure 6: (a) Operating and failure regions through proposed predictive methodology in the Vdd x Vcs space for case 1: wordline connected to Vdd.

Figure 6: (b) Hardware data for the operating/failure region shows close matching.

Predictive Analytics for High Dimensionality
Historically, high dimension problems pose a special challenge in the field of statistical analysis, so analyses have been generally limited to looking at a limited number of dimensions, with 100 dimensions being a typical limit. However, many chip failure mechanisms may have contributing effects from hundreds or thousands of transistors, and each transistor may have several parameters of interest, resulting in 30,000 or more dimensions. Furthermore, for ease of use, designers would rather not identify the scope of transistors which may impact performance & failure, but rather let the tool perform all the diagnostics, resulting in even more parameters and consequently higher dimensions. To understand why high dimensions pose a special problem, consider the SRAM case of one dimension, where there is typically a perfect correlation between probability of model parameter variation and output variation, as shown in Figure 7. However, in very high dimension spaces, there is no correlation between distance from nominal (likelihood of a sample point), and failure probability of the chip. For example, Figure 7 illustrates a sample case with 1,000 dimensions where distance from nominal has no discernible correlation with failure. Real case data is also presented for a 126 dimension case and it is evident that the pass/fail points are overlapping relative to their distance from nominal. In other words, the fail points cannot be distinguished from the pass points according to likelihood of occurrence of the points. This is a fatal problem for methods that order the Monte Carlo samples by distance to nominal or attempt to perform some sort of filtering of the points by such criteria. Rather, more sophisticated techniques are needed that consider the sensitivity of the failure to each dimension, not only at nominal but also in regions where failures are more likely.

One of the critical aspects of predictive statistical prediction technology is the error control algorithm and ability to monitor and diagnose the tools' convergence. This is particularly critical and challenging for very high sigma application such as that illustrated in Figure 8, where 20,000 samples are required to analyze the tail of the distribution out to 8s. Note, on the right side of Figure 8, the framework provides continuously updated diagnostics about the convergence with upper & lower confidence intervals, versus sample number.

Figure 7: No correlation between distance from nominal (likelihood of a sample point), and failure probability in high dimension (not to scale). Case data with overlapping pass/fail samples.

Figure 8: >7s high sigma analysis for 6T SRAM bitcell

More Stories By Rajiv V. Joshi

Dr. Rajiv V. Joshi is a research staff member at T. J. Watson research center, IBM. He received his B.Tech I.I.T (Bombay, India), M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). His novel interconnects processes and structures for aluminum, tungsten and copper technologies which are widely used in IBM for various technologies from sub-0.5μm to 14nm. He has led successfully pervasive statistical methodology for yield prediction and also the technology-driven SRAM at IBM Server Group. He commercialized these techniques. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for licensing contributions, holds 54 invention plateaus and has over 200 US patents and over 350 including international patents.

Dr. Joshi has authored and co-authored over 175 papers. He is a recipient of 2013 IEEE CAS Industrial Pioneer award and 2013 Mehboob Khan Award from Semiconductor Research corporation. He is Distinguished Lecturer for IEEE CAS and EDS society. He is IEEE and ISQED fellow and distinguished alumnus of IIT Bombay. He serves as an Associate Editor of TVLSI. He served on committees of ISLPED (Int. Symposium Low Power Electronic Design), IEEE VLSI design, IEEE CICC, IEEE Int. SOI conf ISQED and Advanced Metallization Program committees. He is an industry liaison for universities as a part of the Semiconductor Research Corporation.

More Stories By Bruce W. McGaughy

Dr. Bruce W. McGaughy is a Distinguished Engineer, Simulation Chief Architect. He received a BS in Electrical Engineering from the University of Illinois at Urbana/Champaign and an MS and PhD in Electrical Engineering and Computer Science from the University of California at Berkeley, in 1994, 1995 and 1997, respectively. He has conducted and published research in the fields of circuit simulation, device physics, reliability, electronic design automation, computer architecture and fault tolerant computing. Prior to his current assignment, he worked for Integrated Device Technolgy (IDT), Siemens, Intel, Berkeley Technology Associates, and Celestry. In 2003, Dr. McGaughy was the group director in charge of circuit simulation R&D at Cadence, including Spectre, SpectreRF and UltraSim.

In 2006, Dr. McGaughy became the distinguished engineer and chief architect for Cadence simulation products, including Spectre, SpectreRF, UltraSim and AMS Designer. In 2008, he joined ProPlus Design Solutions as the Senior VP of Engineering and Chief Technology Officer. He is in charge of all of ProPlus R&D efforts, including the BsimProPlus model extraction platform, the NanoSpice parallel spice simulator, and the NanoYield DFY platform.

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